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1. No references found the usage of x86 memory fences.
2. General reference for memory ordering (aka. memory consistency), recommended in "A Quantitative Approach" by Henneessy and Patterson:
    http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-95-7.pdf
3. x86 (IA-32) memory ordering
   1. Analysis is seen in "A Better x86 Memory Model: x86-TSO":
         http://www.springerlink.com/content/f7717l1275624610/
   2. x86 (IA-32) memory ordering seems to be little confused by seeing Table 1. "Summary of Memory Ordering" in : 
         http://www.ee.ryerson.ca/~courses/coe518/LinuxJournal/elj2005-136-memoryordering1.pdf
      The memory ordering is relaxed from SC->TSO->PSO->WO. X86 still keeps W->W order even R->RW order is relaxed. The atomic operations in x86 also seem to work as a memory fence, which is different from other CPU architectures.
   3.  The memory ordering of x86 is also discussed in section 2 of "A Better x86 Memory Model: x86-TSO":
       http://www.springerlink.com/content/f7717l1275624610/
       Notice that the memory consistency model in Intel and AMD is not identical.
4. In case of MIPS R10000)
   1. R10k guaranteed sequential consistency (SC) with speculative execution mechanism for software compatibility. The design seems successful although it might limit wider instruction issue with more than two load/store pipelines. Wider instruction issue is not common because of diminishing return of Instruction Level parallelism.
      Hill also recommends R10000's approach:
       http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=707614;
      (We can download this paper for free in google scholar.)
   2. R10k has 'sync' instruction. It is just for waiting emptying the external memory (write) buffers and for synchronizing to special uncached operation named 'uncached accelerated' mainly used for accelerating command filling to peripheral such as a graphic engine, etc.