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Modern TLB Characteristics
NB: Purportedly the new Westmere Nehalem chips have GB pages
Opteron (K10) and Nehalem have split L1 and L2 TLBs. In both cases, the L1 TLB consists of separate instruction (ITLB) and data TLBs. The Nehalem has a unified L2 TLB, unlike the Opteron.
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The Opterons do not support 1G pages in their ITLBs, so code in 1G mappings is to be avoided. This shouldn't be an issue.
- Xeon (Nehalem):
- 64-entry fully4-way set-associative L1 data TLB for 4K pages
- 32-entry fully4-way set-associative L1 data TLB for 2M and 4M pages
- supports 4K, 2M and 4M pages. NO 1G PAGES
- 512-entry unified 4-way set-associative L2 TLB, which only supports 4K pages
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